The present invention generally relates to magnetic tunnel junction (MTJ) structures, and more specifically, to magnetic tunnel junction structures configured for integrated chip (IC) identification.
Integrated circuit (IC) chip cloning and counterfeiting are recurrent issues in many areas, and in particular, in the area of semiconductors. These issues can cost billions of dollars in revenue. Used chips are often still functional and are reused and resold after de-soldering, thereby putting the chips back into the supply chain. Such practices can pose reliability and security risks. In addition, the chips can be cloned or copied, thereby posing additional security risks. Companies often do not report counterfeit chips when they find them. Moreover, some of the reused chips can be found in military hardware, further imposing significant security risks and exposure.
Current methods of integrated circuit (IC) chip identification include eFUSE devices. Such devices are currently used in consumer parts to “mark” chips. eFUSE devices store a bit string that is authenticated at “power on”. eFUSE can be easily visible with routine inspection techniques. In some instances, the marking or the unique bit string can be easily read, imaged and copied many times. Accordingly, chips with eFUSE and other conventional means of authentication can be easily cloned and may pose security issues.
Other technologies include static random access memory (SRAM) based identification systems. The power-up of the SRAM cell depends on the Vt fluctuation which can be used to generate a unique bit string. It is, however, not stable over time, voltage and temperature.
Accordingly, there remains a need for more reliable and secure identification and authentication for greater security in the global supply chain of integrated circuit (IC) chips.